1. Field of the Invention
The present invention relates to a three dimensional stacked nonvolatile semiconductor memory.
2. Description of the Related Art
BiCS (Bit Cost Scalable) technology is known as a technology for suppressing a bit cost of a semiconductor memory by increasing the capacity thereof by a three dimensional structure (refer to, for example, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” 2007 Symposium on VLSI Technology Digest of Technical Papers. p. 14).
A nonvolatile semiconductor memory to which the BiCS technology is applied (hereinafter, called a BiCS memory) has a feature in that it not only has a three dimensional structure but makes bit cost scalability possible so that a bit cost can be reduced in proportion to an increase of the number of stacked layers by devising a device structure and a process technology.
In, for example, a NAND flash memory to which the BiCS technology is applied (hereinafter, called a BiCS-NAND flash memory), a memory capacity, which greatly exceeds the limit of the memory capacity of a NAND flash memory having a two-dimensional structure, can be realized by increasing the number of cells in a longitudinal direction which comprise a NAND column by increasing the number of stacked layers.
However, since the BiCS memory which is represented by a BiCS-NAND flash memory has a unique device structure, there are many problems to be solved to practically use the BiCS memory.
An increase of a peripheral circuit is exemplified as one of the problems.
In the BiCS memory, although a memory cell array is arranged as a three dimensional structure, a peripheral circuit is arranged as a two dimensional structure like a conventional structure. Further, select gate lines on a bit line side must be disposed in one block according to a memory cell array structure specific to the BiCS memory.
Accordingly, in the BiCS memory, the area of drivers for driving the select gate lines on the bit line side is increased by the number of the select gate lines in one block as compared with a nonvolatile semiconductor memory having a two dimensional structure in which it is only necessary to dispose one select gate line in one block.